1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method and apparatus for generating an internal clock signal for a semiconductor device.
2. Description of the Related Art
In a synchronous DRAM semiconductor memory device, each of the internal devices are controlled by an internal clock signal which has the same period as an external clock signal which is applied to the device. An internal clock generation circuit generates the internal clock signal in response to the external clock signal.
FIG. 1 is a block diagram of a conventional internal clock generation circuit for a synchronous DRAM semiconductor device. Referring to FIG. 1, the internal clock generation circuit includes a clock buffer 13 for receiving an external clock signal CLK, and an internal clock generation unit 15 for receiving the output of the clock buffer 13 to generate an internal clock signal PCLK.
The external clock signal is applied as a transistor-transistor logic (TTL) level signal. Since all signals of the synchronous DRAM semiconductor device 11 operate at a CMOS level, the clock buffer 13 converts the TTL level external clock signal into a CMOS level signal. The internal clock generation unit 15 generates the internal clock signal PCLK in response to the external clock signal which has been converted to a CMOS level.
FIG. 2 is a circuit diagram of the internal clock generation unit 15 shown in FIG. 1. Referring to FIG. 2, the internal clock generation unit 15 has first through fifth inverters 21, 22, 23, 24 and 25 which are connected in series with the output of the clock buffer 13 of FIG. 1, and delays the output of the clock buffer 13 by a predetermined time. The phase of output of the clock buffer 13 is inverted while passing through the fifth inverter 25. The output of the fifth inverter 25 and the output of the clock buffer 13 are input into a first NAND gate 27. The output of the first NAND gate 27 is logic low level only when all of the received signals are at a logic high level. The output of the first NAND gate 27 is connected to sixth through eighth inverters 29, 30 and 31, which stabilize the signal generated by the first NAND gate 27. The output of the first NAND gate 27 is inverted by the eighth inverter 31. The internal clock signal PCLK is generated by the eighth inverter 31.
FIG. 3 is a circuit diagram of the clock buffer 13 of FIG. 1. The clock buffer 13 includes a differential amplifier 33 which receives the external clock signal CLK and a reference voltage VREF of 1.4 volts. The differential amplifier 33 includes a first PMOS transistor 35 having a source connected to a CMOS level power supply voltage Vdd and a grounded gate, second and third PMOS transistors 37 and 39 connected to the first PMOS transistor 35, and first and second NMOS transistors 41 and 43 connected between the second and third PMOS transistors 37 and 39 the ground voltage GND. The output of the differential amplifier 33 is generated at a node at which the third PMOS transistor 39 is connected to the second NMOS transistor 43.
The differential amplifier 33 outputs the power supply voltage Vdd when the voltage of the external clock signal CLK is higher than the reference voltage VREF, and outputs the ground voltage GND when the voltage of the external clock signal CLK is lower than the reference voltage VREF.
In order to control the differential amplifier 33, the output of the differential amplifier is connected to ninth and tenth inverters 45 and 47, and to a second NAND gate 49. A control signal PCKE is input to the second NAND gate 49. When the control signal PCKE is logic low, the output of the second NAND gate 49 is logic high, and when the control signal PCKE is logic high, the output of the second NAND gate 49 is the same as the output of the tenth inverter 47, but inverted.
FIG. 4 is a timing diagram illustrating the operation of the internal clock generation circuit of FIG. 1. When the CSB signal is enabled to a logic low level, an external command COM is input, thereby activating the synchronous DRAM semiconductor device 11. Even after the CSB signal is disabled to a logic high level, the synchronous DRAM semiconductor device 11 is in an active state. When the CSB signal goes low again, another command which specifies a reading or writing operation is input into the synchronous DRAM semiconductor device 11.
The internal clock generation circuit shown in FIG. 1 generates an internal clock signal PCLK whenever the external clock signal CLK is triggered to a logic high level regardless of the state of the CSB signal and the command COM. However, the synchronous DRAM semiconductor device 11 performs an active operation and read and write operations only when the CSB signal is enabled. Accordingly, only the pulses P0 and P4 pulses of the internal clock signal PCLK shown in FIG. 4 are required. However, all of the pulses P1, P2, P3, P5, P6, P7 and P8 are generated by the conventional internal clock generation circuit, thereby increasing the power consumption of the device. This, in turn, causes many internal portions of the synchronous DRAM semiconductor device which are controlled by the internal clock signal PCLK to operate in response to the unnecessary pulses which further increases power consumption.